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Opteron 64 or Intel PIV with 800MHz FSB?
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Thread: Opteron 64 or Intel PIV with 800MHz FSB?

  1. #1
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    Opteron 64 or Intel PIV with 800MHz FSB?

    I can't decide here. My local shop is offering the same price for either Opteron 64 3.2 GHz or Intel 3.2 GHz with 800 FSB and HyperThreading. Pros and Cons?

  2. #2

    Re:Opteron 64 or Intel PIV with 800MHz FSB?

    Same clock speed, but one 32bit and one 64? I'm willing to guess the bus speed on the opteron is 1600 also...

  3. #3
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    Re:Opteron 64 or Intel PIV with 800MHz FSB?

    I haven't checked out the MB so I'm not sure what FSB would be. The major thing that I am not going AMD32 chips are that their MBs are of 333MHz the highest I've seen. Some new boards may be 400MHz depending on the setup I think.

    I'm going after FSB since I will be running business intensive programs and graphic rendering such as 3D images and videos on test environment. I'm investing in 10K RPM Seagate 40 GB SCSI drive so I"m going after high-end throughput, disk intensive processes.

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    Re:Opteron 64 or Intel PIV with 800MHz FSB?

    The Front Side Bottleneck and Shared I/O

    A major focal point in the problem of the traditional chipset design begins with the term known as the Front Side Bus (FSB). The FSB suggests that there is only a single point of system interconnect between the CPU and the rest of the system (with the Back Side Bus, BSB, on the chip itself). The CPU connects to the northbridge, a single bus between all other components that means only two system components can talk to each other at any time. Furthermore, it means that the CPU, memory, and bridges run synchronously, possibly with associated timing and stability issues. In server space, this is nothing less than a "Front Side Bottleneck".
    ___________________________
    The key to Opteron 200/800 scalability is in the additional HyperTransport channels for CPU-to-CPU interconnect. It is not merely a switching system interconnect versus a bus (as Alpha/Athlon EV6 is to Intel [A]GTL+); each CPU has direct connections to its own memory, other CPUs, and then I/O. To draw an analogy to Ethernet: AGTL+ (Xeon MP) systems are connected to each other, to memory, and to I/O all through the same Ethernet hub; EV6 (Athlon MP) is like having an Ethernet switch; and NUMA/HyperTransport (Opteron) is like having direct Ethernet connections between (no hub or switch).

    The memory connections are direct, glue-less, 184-pin DDR SDRAM channels directly connected to the chip. There is one DDR channel in Socket-754 and two DDR channels in Socket-939/940 (noting that 754+184=938, there are two, true, full, non-multiplexed DDR buses in the case of Socket-939/940). There are several advantages to this. One is the fact that memory speed no longer limits the performance of any other interconnect. In other words, the memory clock is its own, independent divider of the local CPU clock -- separate from all others, including I/O. Using DDR266/PC2100 (2.1 GBps/channel) instead of DDR400/PC3200 (3.2 GBps/channel) makes no impact on the CPU speed or HyperTransport clocks. And, it gets better.

    In proprietary NUMA Xeon MP, if a program on one CPU needs to access the memory located on another, it must use the shared, old-style FSB between CPUs. Not only does only one CPU access that bus at a time, but it prevents any other transfer -- CPU to/from memory to/from I/O -- from occurring. In HyperTransport Opteron, each CPU has a dedicated connection to another CPU (or within one hop of another, in the case of Opteron 800), so there is no (or limited) contention with other memory, CPU, or I/O transfers.


    http://www.samag.com/documents/s=940...411b/0411b.htm

    Not only that, but if you have to access >4G ram, opteron or AMD64 can do it without PAE, meaning less OS overhead. I assume its a xeon with hyperthreading, not a itaneum.

  5. #5

    Re:Opteron 64 or Intel PIV with 800MHz FSB?

    [quote author=Radar link=board=3;threadid=9963;start=0#msg90380 date=1100042766]
    The Front Side Bottleneck and Shared I/O

    A major focal point in the problem of the traditional chipset design begins with the term known as the Front Side Bus (FSB). The FSB suggests that there is only a single point of system interconnect between the CPU and the rest of the system (with the Back Side Bus, BSB, on the chip itself). The CPU connects to the northbridge, a single bus between all other components that means only two system components can talk to each other at any time. Furthermore, it means that the CPU, memory, and bridges run synchronously, possibly with associated timing and stability issues. In server space, this is nothing less than a "Front Side Bottleneck".
    ___________________________
    The key to Opteron 200/800 scalability is in the additional HyperTransport channels for CPU-to-CPU interconnect. It is not merely a switching system interconnect versus a bus (as Alpha/Athlon EV6 is to Intel [A]GTL+); each CPU has direct connections to its own memory, other CPUs, and then I/O. To draw an analogy to Ethernet: AGTL+ (Xeon MP) systems are connected to each other, to memory, and to I/O all through the same Ethernet hub; EV6 (Athlon MP) is like having an Ethernet switch; and NUMA/HyperTransport (Opteron) is like having direct Ethernet connections between (no hub or switch).

    The memory connections are direct, glue-less, 184-pin DDR SDRAM channels directly connected to the chip. There is one DDR channel in Socket-754 and two DDR channels in Socket-939/940 (noting that 754+184=938, there are two, true, full, non-multiplexed DDR buses in the case of Socket-939/940). There are several advantages to this. One is the fact that memory speed no longer limits the performance of any other interconnect. In other words, the memory clock is its own, independent divider of the local CPU clock -- separate from all others, including I/O. Using DDR266/PC2100 (2.1 GBps/channel) instead of DDR400/PC3200 (3.2 GBps/channel) makes no impact on the CPU speed or HyperTransport clocks. And, it gets better.

    In proprietary NUMA Xeon MP, if a program on one CPU needs to access the memory located on another, it must use the shared, old-style FSB between CPUs. Not only does only one CPU access that bus at a time, but it prevents any other transfer -- CPU to/from memory to/from I/O -- from occurring. In HyperTransport Opteron, each CPU has a dedicated connection to another CPU (or within one hop of another, in the case of Opteron 800), so there is no (or limited) contention with other memory, CPU, or I/O transfers.


    http://www.samag.com/documents/s=940...411b/0411b.htm

    Not only that, but if you have to access >4G ram, opteron or AMD64 can do it without PAE, meaning less OS overhead. I assume its a xeon with hyperthreading, not a itaneum.
    [/quote]

    Thanks for the info! Very interesting!

  6. #6
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    Re:Opteron 64 or Intel PIV with 800MHz FSB?

    [quote author=Radar link=board=3;threadid=9963;start=0#msg90380 date=1100042766]
    The memory connections are direct, glue-less, 184-pin DDR SDRAM channels directly connected to the chip. There is one DDR channel in Socket-754 and two DDR channels in Socket-939/940 (noting that 754+184=938, there are two, true, full, non-multiplexed DDR buses in the case of Socket-939/940).[/quote]
    I know that having two DDR channel would be a good thing but what drawback will have by having only one DDR channel? The MB I'm looking at ( MSI K8Neo Platinum ) is socket 754. It will have Athlon64 2800+.

    There are several advantages to this. One is the fact that memory speed no longer limits the performance of any other interconnect. In other words, the memory clock is its own, independent divider of the local CPU clock -- separate from all others, including I/O.
    Is it true for both or is it the case only with socket 939?

    Using DDR266/PC2100 (2.1 GBps/channel) instead of DDR400/PC3200 (3.2 GBps/channel) makes no impact on the CPU speed or HyperTransport clocks. And, it gets better.
    So only the size of the memory is the major deciding factor? If the price of 512MB DDR400 is the same as 1 GB DDR266, then it's much more cost worthy to go for 1 GB stick?
    Not only that, but if you have to access >4G ram, opteron or AMD64 can do it without PAE, meaning less OS overhead. I assume its a xeon with hyperthreading, not a itaneum.
    This is one huge mistake Intel made with Itanium. DEC never was successful with Alphas (okay I admit; everyone WANTS an Alpha and dream to have one but the price was humongus at that time). So there is almost no support for pure 64 bits. By having a chip that can take both 32 bits and 64 bits made AMD to capture a lot of market share while Intel was playing catch up on this sector. So the only variable option people have now if you want to run some 64 bits is to go with AMD, I guess.

    [off-topic: One guy I talked to at the store looking at the boards told me that he run 64 bits version of Windows on his 3200+ box. I was like "dude, don't lie to me, windows don't have 64 bits except Alpha" and he was like "no, I have at home, it has IE and Windows on it and that's it, no network, no internet". I was like you must be [bashing]exclusive windows user[/bashing]". hehheheeheh ........... so I told him that SuSE and Red Hat Enterprise versions both support 64 bits. He told me he would check it out but I doubt it.[/off-topic]

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